1. Technical Field
The present invention relates to a voltage detector for power supply voltage, and more particularly, to a voltage detector for use in power-on-reset (POR) circuitry that generates a reset signal to initialize circuit components upon detecting a power supply voltage rising to a given set point during power-up, which may be implemented on a semiconductor integrated circuit for incorporation into various electronic devices, such as mobile phones and laptop computers.
2. Description of the Background Art
Voltage detectors are employed in power-on-reset (POR) circuitry to generate a reset signal upon detecting a power supply voltage rising to a given set point during power-up, which initializes electrical components, such as flip-flops, latches, counters, registers, etc., forming a central processing unit (CPU) of the system. Typically, a POR circuit with voltage detection capabilities is implemented on a semiconductor integrated circuit for incorporation into various electronic devices, such as mobile phones and laptop computers.
FIG. 1 is a circuit diagram schematically illustrating a conventional voltage detector 104.
As shown in FIG. 1, the voltage detector 104 includes an input terminal to receive an input voltage VIN, a power supply terminal to receive a power supply voltage VDD1, and an output terminal to output an output signal DOUT, as well as a step-down voltage regulator 103, a voltage detection circuit 101, and output circuitry formed of a pair of first and second, constant current sources 115 and 117, a pair of first and second output transistors 116 and 118, each being an N-channel metal-oxide semiconductor (NMOS) device, and an inverter or logic NOT gate 131.
In the voltage detector 104, the step-down voltage regulator 103 is connected to the power supply terminal to convert the power supply voltage VDD1 into a lower, regulated supply voltage VDD2 for supply to the voltage detection circuit 101 and the output circuitry.
The voltage detection circuit 101 includes a set of voltage divider resistors 111 through 113 connected in series between the input terminal and ground to output a sense voltage VINS at a node between the resistors 111 and 112 proportional to the input voltage VIN, and an NMOS transistor switch 130 connected in parallel with the grounded resistor 113. Also included are a reference voltage generator 114 to generate a reference voltage Vref based on the power supply voltage VDD1, and a comparator 110 that receives the sense voltage VINS at an inverting input thereof and the reference voltage Vref at a non-inverting input thereof to generate a result of comparison between the input voltages VINS and Vref for output to the gate terminal of the transistor 116.
In the output circuit, the first constant current source 115 and the first output transistor 116 are connected in series between the supply voltage VDD2 and ground, with a node therebetween connected to the gate terminal of the transistor 118. The second constant current source 117 and the second output transistor 118 are connected in series between the supply voltage VDD2 and ground, with a node therebetween connected to the input terminal of the inverter 131. The output of the inverter 131 constitutes the output terminal of the voltage detector 104.
During operation, the voltage detector 104 outputs a reset signal or pulse DOUT when the input voltage VIN rises to a sufficient level for initialization during power-on, wherein the voltage detection circuit 101 monitors the input voltage VIN to cause the comparator 110 to switch its logic state whenever the input voltage VIN reaches a set point voltage Vdet, which is relatively high (“reset threshold Vdet+”) where the voltage VIN rises from a lower level, and relatively low (“detection threshold Vdet−”) where the voltage VIN falls from a higher level.
A problem encountered by the conventional voltage detector 104 is that it can incorrectly output a reset signal DOUT where the input voltage VIN does not reach the reset threshold Vdet+ during power-on. To illustrate the problem, consider a situation where the input voltage VIN rises to a level between the detection voltage Vdet− and the reset voltage Vdet+ prior to the power supply voltage VDD1 rising to a level sufficient to activate the detection circuit 101 powered with the regulated supply voltage VDD2.
In such cases, the voltage divider resistors 111 through 113 generate a sense voltage VINS from the input voltage VIN before the reference voltage generator 114 generates a reference voltage Vref from the supply voltage VDD1. The comparator 110, receiving the relatively high inverting input VINS and the relatively low non-inverting input Vref upon activation, outputs a logic low signal. The detection signal thus generated turns off the transistor 116 to in turn cause the transistor 118 to turn on and then the transistor 130 to turn off, resulting in the voltage detector 104 incorrectly outputting a reset pulse DOUT where the reset threshold Vdet+ has not been reached during power-on.
Hence, for proper operation of the voltage detector 104, the power supply voltage VDD1 for activating the comparator 110 is required to reach a specified level before the voltage divider circuit outputs the sense voltage VINS by dividing the input voltage VIN. Such requirement limits the availability of the voltage detector 104, making the conventional method less practical than otherwise expected.
To date, several other conventional methods have been proposed to provide an effective voltage detector for detecting a power supply voltage to generate a reset signal.
For example, one conventional method provides a voltage detector that detects an input voltage based on a hysteresis comparator provided with a reset threshold Vdet+ and a detection threshold Vdet−, the former being higher than the latter by a given threshold voltage. The hysteresis comparator is equipped with a hysteresis voltage controller that periodically reduces the hysteresis voltage during power-on, so as to enable the comparator to output a reset pulse when the input voltage exceeds the detection threshold Vdet− but does not yet reach the reset threshold Vdet+. Once the initial reset pulse is released, the hysteresis voltage controller returns the hysteresis voltage to the original level so that the comparator no longer outputs a reset pulse unless the reset threshold Vdet+ is reached.
According to this method, the voltage detector can generate a reset signal when the input voltage reaches the relatively low threshold Vdet− instead of the relatively high threshold Vdet+ during power-on. Such capability may be used to remove variability from a reset signal that can be occasionally released whether the input voltage reaches a detection threshold Vdet− or a reset threshold Vdet+ depending on the rising edge or other characteristics of the input voltage during power-on. However, the method can cause incoherence in the system and therefore is not reasonably practical, considering that a reset signal is required to indicate whenever the reset threshold Vdet+ is reached regardless of whether it is output during or after power-on, so as to serve its intended purposes.
Another conventional method provides a voltage detector that generates a primary detection signal upon detecting a power supply voltage falling below a given detection threshold through a primary detection circuit employing a bandgap reference (BGR) circuit for reference voltage generation. The BGR-based primary detection circuit is used in combination with a secondary detection circuit formed of a series circuit composed of a resistor and a MOS transistor, which retains the logic state of the primary detection signal upon detecting the power supply voltage falling below a setpoint voltage lower than the threshold voltage.
Such dual-detector circuitry is designed to address a problem encountered when using a BGR voltage in voltage detection, wherein the BGR circuit, when supplied with a low power supply voltage, outputs an unstable reference voltage which is repeatedly reached by a monitored voltage, resulting in unreliable operation of the BGR-based voltage detector. According to this method, provision of the secondary detection circuit periodically invalidates the primary detection circuit where the BGR circuit is unstable, thereby ensuring the voltage detector reliably operates with lower supply voltages.
Although effective for its intended purposes, the conventional voltage detector fails to work properly when used in high-voltage applications where a step-down voltage regulator renders a power supply voltage into a lower, regulated voltage. That is, the voltage detector can improperly switch its output signal as the secondary detection circuit detects the regulated power supply voltage transiently falling below the setpoint voltage due to variations in the power supply voltage even though the power supply voltage still remains above the threshold voltage.